Redistribution in wafer level chip size packaging technology for high power device applications: Process and design considerations

The main investigation presented in this work is focused on the design and fabrication of redistribution in wafer level chip scale package (RDL in WLCSP) for high power device application. The design considers higher carrier loading incorporated with the dimensional broadening in both lateral and thickness direction of the metal redistribution layer. The lateral broadening shortens the channels of electrical isolation, while the thickness broadening evolves the conventional sputtering into the present electro-plating achieved Cu metallization layer. The innovation brings about the challenge for high power RDL in WLCSP. In this study, the interplay between structural design, process interactions, and possible solutions for high power RDL in WLCSP are presented. To address the arguments, two designs of experiment are conducted. We demonstrate the determinative influence factors, resultant from process interactions, toward the adhesive properties beyond the conventional wisdom.