Formal verification of embedded logic controller specification with computer deduction in temporal logic

The article presents a novel approach to formal verification of logic controller specification. Model checking technique is used to verify some behavioral properties. The approach proposes to use a rule-based logical model presented at RTL-level. Proposed logical model is suitable both for formal verification (model checking in the NuSMV tool) and for logical synthesis (using hardware description language VHDL). As the result, logic controller program (its implementation) will be valid according to its primary specification. Streszczenie. Artykul przedstawia nowatorskie podejście do formalnej weryfikacji specyfikacji sterownika logicznego. Zaproponowany zostal regulowy model logiczny, ktory jest dogodny zarowno do formalnej weryfikacji (weryfikacja modelowa w narzedziu NuSMV), jak rowniez do syntezy logicznej (z uzyciem jezyku opisu sprzetu VHDL). Program sterownika logicznego (jego implementacja) bedzie zatem poprawny wzgledem początkowej specyfikacji. (Formalna weryfikacja specyfikacji wbudowanych sterownikow logicznych z wykorzystaniem wnioskowania komputerowego w logice temporalnej).

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