Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques

Branch-and-bound approaches are promising in pruning fruitless search space during the resource constrained scheduling. However, such approaches only compare the estimated upper and lower bounds of an incomplete schedule to the length of the best feasible schedule at that iteration, which does not fully exploit the potential of the pruning during the search. Aiming to improve the performance of resource constrained scheduling, this paper proposes a parallel structure-aware pruning approach that can traverse the search space significantly faster than state-of-the-art branch-and-bound techniques. This paper makes three major contributions: i) it proposes an efficient pruning technique using the structural scheduling information of the obtained best feasible schedules; ii) it investigates how to perform parallel search to enable efficient multi-directional search and generation of effective fences by tuning the operation enumeration order; and iii) it presents a framework that supports the sharing of minimum upper-bound and fence information among different search tasks to enable efficient parallel structure-aware pruning. The experimental results demonstrate that our parallel pruning approach can drastically reduce the overall resource constrained scheduling time under a wide variety of resource constraints.

[1]  Montek Singh,et al.  A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems , 2010, 2010 IEEE Symposium on Asynchronous Circuits and Systems.

[2]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[3]  J. Ramanujam,et al.  A fast approach to computing exact solutions to the resource-constrained scheduling problem , 2001, TODE.

[4]  Giri Tiruvuri,et al.  Estimation of lower bounds in scheduling algorithms for high-level synthesis , 1998, TODE.

[5]  Jason Cong,et al.  High-Level Synthesis for FPGAs: From Prototyping to Deployment , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Mingsong Chen,et al.  Branch-and-bound style resource constrained scheduling using efficient structure-aware pruning , 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[7]  Minjoong Rim,et al.  Lower-bound performance estimation for the high-level synthesis scheduling problem , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Daniel Gajski,et al.  Introduction to high-level synthesis , 1994, IEEE Design & Test of Computers.

[9]  Sheng-De Wang,et al.  An in-place search algorithm for the resource constrained scheduling problem during high-level synthesis , 2010, TODE.

[10]  André Rossi,et al.  Tabu Search for Multiprocessor Scheduling: Application to High Level Synthesis , 2011, Asia Pac. J. Oper. Res..

[11]  Mohamed I. Elmasry,et al.  Global optimization approach for architectural synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  ShenZhaoxuan,et al.  Lower Bound Estimation of Hardware Resources for Scheduling in High—Level Synthesis , 2002 .

[13]  Forrest Brewer,et al.  Automata-Based Symbolic Scheduling for Looping DFGs , 2001, IEEE Trans. Computers.

[14]  Lei Zhou,et al.  Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis , 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[15]  Gary Smith,et al.  High-Level Synthesis: Past, Present, and Future , 2009, IEEE Design & Test of Computers.

[16]  Prithviraj Banerjee,et al.  Parallel algorithms for force directed scheduling of flattened and hierarchical signal flow graphs , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[17]  Marco Spuri,et al.  Implications of Classical Scheduling Results for Real-Time Systems , 1995, Computer.

[18]  Ghassan Shobaki,et al.  Optimal trace scheduling using enumeration , 2009, TACO.

[19]  Lei Zhou,et al.  Efficient Two-Phase Approaches for Branch-and-Bound Style Resource Constrained Scheduling , 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

[20]  Jason Cong,et al.  Synthesis Algorithm for Application-Specific Homogeneous Processor Networks , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Teodor Gabriel Crainic,et al.  Parallel Branch‐and‐Bound Algorithms , 2006 .

[22]  Mandy Eberhart High Level Synthesis Introduction To Chip And System Design , 2016 .

[23]  A. H. Timmer,et al.  Execution interval analysis under resource constraints , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).