A hardware acceleration scheme for memory-efficient flow processing

This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the flow match limitations in packet throughput, number of supported flows and number of packet header fields (or tuples) supported for flow identifications. The described architecture has been prototyped for accommodating 8 million flows, and tested on an FPGA platform achieving a minimum of 70 million lookups per second. This is sufficient to process internet traffic flows at 40 Gigabit Ethernet.

[1]  Yuan-Sun Chu,et al.  ASIC design of fast IP-lookup for next generation IP router , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[2]  John W. Lockwood,et al.  Deep packet inspection using parallel bloom filters , 2004, IEEE Micro.

[3]  Xin Yang,et al.  Implementation of a network flow lookup circuit for next-generation packet classifiers , 2012, 2012 IEEE International SOC Conference.

[4]  Eli Upfal,et al.  Balanced Allocations , 1999, SIAM J. Comput..

[5]  YunZhao Li.  Non-collision Hash Scheme Using Bloom Filter and CAM , 2009, 2009 Second Pacific-Asia Conference on Web Mining and Web-based Application.

[6]  Yu Hua,et al.  Using Parallel Bloom Filters for Multiattribute Representation on Network Services , 2010, IEEE Transactions on Parallel and Distributed Systems.

[7]  Surin Kittitornkun,et al.  Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPS , 2007, 2007 International Conference on Field-Programmable Technology.

[8]  Michael Mitzenmacher,et al.  The Power of One Move: Hashing Schemes for Hardware , 2008, IEEE/ACM Transactions on Networking.

[9]  Rabi N. Mahapatra,et al.  A Power and Throughput-Efficient Packet Classifier with n Bloom Filters , 2011, IEEE Transactions on Computers.

[10]  Andrei Broder,et al.  Network Applications of Bloom Filters: A Survey , 2004, Internet Math..