FPGA implementation of polar code based encoder architecture

Polar codes, introduced by Arikan, achieves the capacity of symmetric channels with “low encoding and decoding complexity” for a large class of underlying channels. Recently, polar code has become the most favourable error correcting code in the viewpoint of information theory due to its property of channel achieving capacity. Although the fully parallel polar code based encoder architecture processes the bits in a fully parallel fashion but suffers with huge hardware complexity with increasing code length. As fully parallel polar code based architecture will cause logic complexity problem, while partial parallel polar code based architecture is limited by memory units of high-throughput applications. In this paper, efficient polar code based encoder architecture is designed and implemented on a FPGA using Vertex 5 for the polar encoding scheme. Here we analyse the encoding process of polar code based encoder architecture and propose a new architecture that is suitable for encoding long polar codes with less hardware complexity.