A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology

This paper presents a time-to-digital (TDC) design with large detectable range and fine resolution, combining a ring TDC with a 2-dimentional (2D) Vernier TDC. The detectable range has been greatly increased to 14 bits with the ring structure. A 1-ps resolution was achieving with 2D Vernier architecture. Utilizing the 2nd order ΔΣ modulators (SDM) and a 2D spiral arbiter array, the proposed TDC greatly mitigates the quantization errors introduced by digitally controlled delay cells and the intrinsic arbiter line folding errors associated with the 2D array topology. The measured maximum DNL/INL are 0.41/0.79ps with ΔΣ linearization. A prototype TDC chip fabricated in 130nm CMOS technology achieves a conversion rate of 10 MS/s while consumes 2.4 mW power.

[1]  Giovanni Marzin,et al.  A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power , 2012, IEEE Journal of Solid-State Circuits.

[2]  Fa Foster Dai,et al.  A 12-bit vernier ring time-to-digital converter in 0.13μm CMOS technology , 2009, 2009 Symposium on VLSI Circuits.

[3]  Foster F. Dai,et al.  A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[4]  Hua Wang,et al.  A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization , 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

[5]  Taeik Kim,et al.  A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[6]  Kathleen Philips,et al.  9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[7]  Satoshi Kondo,et al.  19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[8]  Sangwook Han,et al.  24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and −78dBc fractional spur for cellular RFICs , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[9]  Giovanni Marzin,et al.  A 20Mb/s phase modulator based on a 3.6GHz digital PLL with −36dB EVM at 5mW power , 2012, 2012 IEEE International Solid-State Circuits Conference.

[10]  Antonio Liscidini,et al.  Two-Dimensions Vernier Time-to-Digital Converter , 2010, IEEE Journal of Solid-State Circuits.

[11]  Taeik Kim,et al.  15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.