PURPOSE: To practically remove a problem, such as the lowering of a logic level accompanied heretofore and to obtain a device having small dimensions with low power and low voltage. CONSTITUTION: A precharge transistor 30 is connected to a voltage supply source, and this supply source is clocked by a 1st clock phase C1. A 1st node A is formed by connecting a discharge transistor 32 to the precharge transistor 30, this discharge transistor 32 is clocked by a 2nd clock phase C2 and discharging the 1st node A with a condition. The precharge transistor 30 precharges the 1st node A. an input logic device 34 forms a 2nd node B by being connected to the discharge transistor 32, and forms a discharge path from the 1st node A to a ground potential. The input logic device 34 is connected so as to receive an input signal, and an output transistor 36 generates a delayed output signal.