Area Efficient Design of Routing Node for Network-on-Chip

Network-on-Chip (NoC) is a paradigm proposed to satisfy the communication demands of future Systems-on-Chip (SoC). The main components of an NoC are the network adapters, routing nodes, and network interconnect links. Reducing area and power consumption has higher priority in the case of on-chip networks compared to conventional off-chip networks. This paper presents an area efficient design for the routing node component of an NoC. T he area efficiency is obtained by applying the concept of a pipelined design as well as the use of custom IP (intellectual property) cores.

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