A 10-bit 5-Msample/s CMOS two-step flash ADC

A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

[1]  K. Maio,et al.  A 10b 20mhz Two-Step Parallel ADC with Internal S/H , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[2]  D.J. Allstot.  A precision variable-supply CMOS comparator , 1982, IEEE Journal of Solid-State Circuits.

[3]  A. Dingwall,et al.  An 8-MHz CMOS subranging 8-bit A/D converter , 1985, IEEE Journal of Solid-State Circuits.

[4]  A.G.F. Dingwall,et al.  Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter , 1979, IEEE Journal of Solid-State Circuits.

[5]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[6]  H. Sato,et al.  An 8b 20mhz Cmos Half-Flash A/D Converter , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[7]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .

[8]  A. Yukawa,et al.  A CMOS 8-Bit High-Speed A/D Converter IC , 1984, IEEE Journal of Solid-State Circuits.

[9]  Masao Nakaya,et al.  An 8-bit high-speed CMOS A/D converter , 1986 .