Effects of high field stresses on threshold voltage of CMOS transistors

Abstract In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n -channel MOSTs decreases, while threshold voltage of p -channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n -channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p -channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n -channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.