A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS

A fully integrated K-band dual down-conversion receiver for phased array radar applications in 90 nm CMOS is presented. The receiver utilizes the dual down-conversion architecture to achieve superior performance. The integrated 1.15 GHz image-rejection filter (IRF) provides enough wideband (22 MHz) image rejection ratio at 140 MHz offset before the second down-conversion by utilizing the $Q$ -enhancing and frequency staggering techniques to compensate the component loss. The low noise amplifier realizes the single-to-differential-ended conversion at the input with a transformer and achieves good common-mode rejection. The 70 MHz intermediate frequency baseband consists of two cascaded 3rd-order band-pass active-RC filters (BPFs) and one automatic gain control (AGC) loop, with the integrator frequency compensation technique to lower down the requirements on the embedded Op-Amps. Two phase-locked loop (PLL) frequency synthesizers are integrated to provide the local oscillation (LO) signals for the down-conversions, where the matching of the charge-pump is improved by adding one extra current compensation branch. The measurements of the prototype show that the receiver converts the targeted mm-wave signal to 70 MHz intermediate frequency while achieving 8.3 dB noise figure (NF), 51–95 dB variable gain range and >45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The receiver draws 74 mA current (excluding 2 PLLs) from the 1.2 V power supplies and occupies a core area of $4.58\times 0.53mm^{2}$ (excluding 2 PLLs).

[1]  Feng Zhao,et al.  An X-Band Radar Transceiver MMIC with Bandwidth Reduction in 0.13 µm SiGe Technology , 2014, IEEE Journal of Solid-State Circuits.

[2]  Baoyong Chi,et al.  1.15 GHz image rejection filter with 45 dB image rejection ratio and 8.4 mW DC power in 90 nm CMOS , 2019, Microelectron. J..

[3]  Yun Chiu,et al.  A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3 , 2015, IEEE Journal of Solid-State Circuits.

[4]  Y. Akazawa,et al.  A low-power wide-band amplifier using a new parasitic capacitance compensation technique , 1990 .

[5]  Hanjun Jiang,et al.  A K-Band Fractional-N Frequency Synthesizer With a Low Phase Noise LC VCO in 90nm CMOS , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[6]  M.J. Deen,et al.  MOSFET modeling for RF IC design , 2005, IEEE Transactions on Electron Devices.

[7]  Gabriel M. Rebeiz,et al.  A $Ku$ -Band Two-Antenna Four-Simultaneous Beams SiGe BiCMOS Phased Array Receiver , 2010, IEEE Transactions on Microwave Theory and Techniques.

[8]  E. Hegazi,et al.  23.4 A Filtering Technique to Lower Oscillator Phase Noise , 2008 .

[9]  F. Svelto,et al.  A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers , 2006, IEEE Journal of Solid-State Circuits.

[10]  Jose Silva-Martinez,et al.  A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors , 2003, IEEE J. Solid State Circuits.

[11]  Yong-Zhong Xiong,et al.  A Ka-Band Single-Chip SiGe BiCMOS Phased-Array Transmit/Receive Front-End , 2016, IEEE Transactions on Microwave Theory and Techniques.

[12]  M. Vadipour,et al.  Capacitive feedback technique for wide-band amplifiers , 1993 .

[13]  Joohwa Kim,et al.  Staggered Gain for 100+ GHz Broadband Amplifiers , 2011, IEEE Journal of Solid-State Circuits.

[14]  Piet Wambacq,et al.  A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  A. Vasilopoulos,et al.  A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR , 2006, IEEE Journal of Solid-State Circuits.

[16]  Gabriel M Rebeiz,et al.  A Two-Channel 8–20-GHz SiGe BiCMOS Receiver With Selectable IFs for Multibeam Phased-Array Digital Beamforming Applications , 2011, IEEE Transactions on Microwave Theory and Techniques.

[17]  M.J. Deen,et al.  A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance used for input matching , 2006, IEEE Microwave and Wireless Components Letters.

[18]  Robert B. Staszewski,et al.  A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection , 2016, IEEE Journal of Solid-State Circuits.

[19]  J.W. Haslett,et al.  2 GHz Automatically Tuned Q-Enhanced CMOS Bandpass Filter , 2007, 2007 IEEE/MTT-S International Microwave Symposium.

[20]  Josef Hausner,et al.  A new Q-enhancement architecture for SAW-less communication receiver in 65-nm CMOS , 2009, 2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).