Enhancing yield at the end of the technology roadmap
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[1] Eric Lindbloom,et al. Structured Logic Testing , 1990 .
[2] Hua Su,et al. A statistical method for reducing systematic defects in the initial stages of production , 2002, 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259).
[3] Kaushik Roy,et al. Skewed CMOS: Noise-immune high-performance low-power static circuit family , 2000, Proceedings of the 26th European Solid-State Circuits Conference.
[4] J. Pineda de Gyvez,et al. On the definition of critical areas for IC photolithographic spot defects , 1989, [1989] Proceedings of the 1st European Test Conference.
[5] J. B. Angell,et al. Redundancy for LSI Yield Enhancement , 1967 .
[6] Jan M. Rabaey,et al. Digital Integrated Circuits: A Design Perspective , 1995 .
[7] Ad J. van de Goor,et al. Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs , 2003, IEEE Trans. Computers.
[8] Kaushik Roy,et al. Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications , 2001, ISLPED '01.
[9] Junichi Hirase. Yield increase of VLSI after redundancy-repairing , 2001, Proceedings 10th Asian Test Symposium.
[10] Xin He,et al. Minimum area layout of series-parallel transistor networks is NP-hard , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] N. O. Sokal,et al. Cause of instability of power amplifier with parallel-connected power transistors , 1984 .
[12] D.M.H. Walker,et al. Circuit-level modeling of spot defects , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.