Vertical MOS technology with sub-0.1 /spl mu/m channel lengths
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Harald Gossner | Ignaz Eisele | F. Wittmann | T. Grabolla | I. Eisele | T. Grabolla | D. Behammer | F. Wittmann | D. Behammer | H. Gossner
[1] R.H. Dennard,et al. Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's , 1987, IEEE Electron Device Letters.
[2] H. Gossner,et al. Vertical Si-Metal-Oxide-Semiconductor Field Effect Transistors with Channel Lengths of 50 nm by Molecular Beam Epitaxy. , 1994 .
[3] T. Ohmi,et al. Dependence of electron channel mobility on Si-SiO/sub 2/ interface microroughness , 1991, IEEE Electron Device Letters.