3D Interconnect technology for space applications

High-density integration of different technologies such as microprocessors, memory, imagers, sensors, RF circuits, ... is a challenge. Current integration based on wire bonding, results in limited interconnect density and often affects performance. Integration on a single substrate (System on a Chip) is technologically complex -if feasible at alland often compromises system performance. A possible solution to both the hybrid integration limitations and the interconnect bottleneck is three-dimensional stacking of dies: "3D integration". The main advantages of such technology are: 1) size/volume reduction, and 2) a higher density of interconnects with lower capacitive and inductive parasitics. Moreover, it allows "seamless" mixing of different microelectronic technologies at the wafer level. The range of possible space applications of 3D stacking is very broad. Particular examples of applications of 3D integration for space are (i) Advanced imagers using through-wafer interconnects and/or wafer thinning, for infrared, visible and X-ray detection, (i i) 3D RF modules, including RF passives and RF-MEMS components, and (iii) Highly miniaturized intell igent sensor nodes, incorporating sensors, read-out electronics, wireless communication and power scavenging. There are generally speaking 3 possible approaches of 3D stacking: (i) 3D-"System-in-a-Package" (3D-SIP): This technique covers the stacking of multiple dies in a single SIP-package and/or the stacking of multiple SIP-packages. The technology is based on flip-chip using solder balls and therefore provides a low interconnect density (10 interconnects/mm2). (ii) 3D-"Wafer level packaging" (3D-WLP): A wafer level packaging technology that includes vertical electrical feedthroughs (vias) going through the (thinned) wafer and as such allows direct stacking of wafers or dies. The 3D interconnects are processed post chip passivation and allow low to medium interconnect density (10-100 int/mm2). (iii) 3D-"Stacked IC" (3D-SIC): The interconnects are processed post Front End and prior to Back End in a modified CMOS process. Using wafer bonding technology, a very high interconnect density (1000 or more int/mm2) is obtained. This paper will present these approaches and their underlying technologies in detail. The relevance of these technologies for space (sensor) systems will also be discussed.