Routability-driven repeater block planning for interconnect-centric floorplanning

In this paper, we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and derive an analytical formula for their computation. We develop a routability-driven repeater clustering algorithm to perform repeater block planning based on iterative deletion. The goal is to obtain a high quality solution for the repeater block locations so that performance-driven interconnect synthesis at the routing stage can be carried out with ease, while minimizing the chip area. Experimental results show that our method increases the percentage of all global nets that meet their target delays from 67.5% in [8] to 85%. Meanwhile, our approach is able to minimize the expected routing congestion, making it easier for performance-driven routers to synthesize global nets that require the insertion of repeaters to meet timing constraints.

[1]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[2]  Yoji Kajitani,et al.  Rectangle-packing-based module placement , 1995, ICCAD.

[3]  Ralph H. J. M. Otten,et al.  Global wires: harmful? , 1998, ISPD '98.

[4]  Martin D. F. Wong,et al.  Closed form solution to simultaneous buffer insertion/sizing and wire sizing , 1997, ISPD '97.

[5]  Jason Cong,et al.  Interconnect delay estimation models for synthesis and design planning , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[6]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .

[7]  Jason Cong,et al.  Performance driven multi-layer general area routing for PCB/MCM designs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[8]  Evangeline F. Y. Young,et al.  Integrated floorplanning and interconnect planning , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[9]  Dhanistha Panyasak,et al.  Circuits , 1995, Annals of the New York Academy of Sciences.

[10]  Eugene Shragowitz,et al.  A global router based on a multicommodity flow model , 1987, Integr..

[11]  Patrick H. Madden.  Partitioning by iterative deletion , 1999, ISPD '99.

[12]  Faming Liang,et al.  Relaxed simulated tempering for VLSI floorplan designs , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[13]  Jason Cong,et al.  Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion , 1996 .

[14]  R. H. J. M. Otten,et al.  Graphs in floor‐plan design , 1988 .

[15]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[16]  Jason Cong,et al.  Challenges and Opportunities for Design Innovations in Nanometer Technologies , 1998 .

[17]  Cheng-Kok Koh,et al.  Routability-driven repeater block planning for interconnect-centricfloorplanning , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Jason Cong,et al.  Buffered Steiner tree construction with wire sizing for interconnect layout optimization , 1996, Proceedings of International Conference on Computer Aided Design.

[19]  Maggie Zhi-Wei Kang,et al.  Delay bounded buffered tree construction for timing driven floorplanning , 1997, ICCAD 1997.

[20]  Jason Cong,et al.  Interconnect design for deep submicron ICs , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[21]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1995, ICCAD.

[22]  Charles J. Alpert,et al.  Wire segmenting for improved buffer insertion , 1997, DAC.

[23]  Ralph Linsker,et al.  An Iterative-Improvement Penalty-Function-Driven Wire Routing System , 1984, IBM J. Res. Dev..

[24]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[25]  Jason Cong,et al.  Buffer block planning for interconnect-driven floorplanning , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[26]  Alberto L. Sangiovanni-Vincentelli,et al.  A Detailed Router Based on Incremental Routing Modifications: Mighty , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  J. Cong,et al.  Interconnect design for deep submicron ICs , 1997, ICCAD 1997.