Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13- μm CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

[1]  M. K. Gowan,et al.  A 65 nm 2-Billion Transistor Quad-Core Itanium Processor , 2009, IEEE Journal of Solid-State Circuits.

[2]  S. Tam,et al.  Clock generation and distribution for the 130-nm Itanium/sup /spl reg// 2 processor with 6-MB on-die L3 cache , 2004, IEEE Journal of Solid-State Circuits.

[3]  Balaram Sinharoy,et al.  POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor , 2011, IEEE Journal of Solid-State Circuits.

[4]  Woogeun Rhee,et al.  Experimental Analysis of Substrate Noise Effect on PLL Performance , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Yu-Chen Wu,et al.  Substrate Noise Coupling Reduction in $LC$ Voltage-Controlled Oscillators , 2009, IEEE Electron Device Letters.

[6]  Tsung-Yi Ho,et al.  Pulsed-Latch Utilization for Clock-Tree Power Optimization , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  David J. Allstot,et al.  Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs , 1993 .

[8]  G. Van der Plas,et al.  On the P+ guard ring sizing strategy to shield against substrate noise , 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

[9]  K. Soumyanath,et al.  Enabling high-performance mixed-signal system-on-a-chip (SoC) in high performance logic CMOS technology , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[10]  A. Iwata,et al.  Isolation strategy against substrate coupling in CMOS mixed-signal/RF circuits , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[11]  Shiro Dosho,et al.  Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs , 2012, IEEE Journal of Solid-State Circuits.

[12]  E. Alon,et al.  The implementation of a 2-core, multi-threaded itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[13]  A. Chandrakasan,et al.  The effect of substrate noise on VCO performance , 2005, 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers.

[14]  Shoichi Masui,et al.  Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits , 1993 .

[15]  A. T. Yang,et al.  Substrate coupling analysis and simulation for an industrial phase-locked loop , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).