III–V Multiple-Gate Field-Effect Transistors With High-Mobility $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ Channel and Epi-Controlled Retrograde-Doped Fin

We report an In<sub>0.7</sub>Ga<sub>0.3</sub>As n-channel multiple-gate field-effect transistor (MuGFET), featuring a lightly doped high-mobility channel with 70% indium and an epi-controlled retrograde-doped fin structure to suppress short-channel effects (SCEs). The retrograde well effectively reduces subsurface punch-through in the bulk MuGFET structure. The multiple-gate structure achieves good electrostatic control of the channel potential and SCEs in the In<sub>0.7</sub>Ga<sub>0.3</sub>As n-MuGFETs as compared with planar In<sub>0.7</sub>Ga<sub>0.3</sub>As MOSFETs. The In<sub>0.7</sub>Ga<sub>0.3</sub>As n-MuGFET with 130-nm channel length demonstrates a drain-induced barrier lowering of 135 mV/V and a drive current exceeding 840 μA/μm at V<sub>DS</sub> = 1.5 V and V<sub>GS</sub> - V<sub>T</sub> = 3 V.

[1]  D. Hisamoto,et al.  A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET , 1989, International Technical Digest on Electron Devices Meeting.

[2]  S. Yoon Growth of strained InGaAs/GaAs by molecular beam epitaxy: a surface morphology, Raman spectroscopy and photoluminescence combined study , 1994 .

[3]  S. Koveshnikov,et al.  Self-Aligned n- and p-channel GaAs MOSFETs on Undoped and P-type Substrates Using HfO2 and Silicon Interface Passivation Layer , 2006, 2006 International Electron Devices Meeting.

[4]  H.C. Lin,et al.  Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric , 2007, IEEE Electron Device Letters.

[5]  T. D. Lin,et al.  Approaching fermi level unpinning in Oxide-In0.2Ga0.8As , 2008, 2008 IEEE International Electron Devices Meeting.

[6]  P. Fejes,et al.  1-$\mu\hbox{m}$ Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm , 2007, IEEE Electron Device Letters.

[7]  P. D. Ye,et al.  High Performance Deep-Submicron Inversion-Mode InGaAs MOSFETs with maximum Gm exceeding 1.1 mS/µm: New HBr pretreatment and channel engineering , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[8]  Yanning Sun,et al.  Scaling of In0.7Ga0.3As buried-channel MOSFETs , 2008, 2008 IEEE International Electron Devices Meeting.

[9]  T. Ma,et al.  Demonstration of unpinned GaAs surface and surface inversion with gate dielectric made of Si3N4 , 2007 .

[10]  G. Bersuker,et al.  InGaAs MOSFET performance and reliability improvement by simultaneous reduction of oxide and interface charge in ALD (La)AlOx/ZrO2 gate stack , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[11]  G. Dewey,et al.  Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[12]  P. Ye,et al.  First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[13]  Daehyun Kim,et al.  30 nm E-mode InAs PHEMTs for THz and future logic applications , 2008, 2008 IEEE International Electron Devices Meeting.

[14]  Guo-Qiang Lo,et al.  A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack , 2008, 2008 IEEE International Electron Devices Meeting.

[15]  Hong,et al.  Epitaxial cubic gadolinium oxide as a dielectric for gallium arsenide passivation , 1999, Science.

[16]  H. Bender,et al.  Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[17]  Y. Yeo,et al.  Silane and Ammonia Surface Passivation Technology for High-Mobility $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ MOSFETs , 2010, IEEE Transactions on Electron Devices.

[18]  F. Horiguchi,et al.  New effects of trench isolated transistor using side-wall gates , 1987, 1987 International Electron Devices Meeting.