An analytical retention model for SONOS nonvolatile memory devices in the excess electron state

We present an analytical retention model for scaled SONOS devices in the excess electron state. In this model, trap-to-band tunneling and thermal excitation discharge mechanisms are considered to be responsible for the temperature-dependent electron decay behaviors in SONOS devices. We assume an arbitrary trap distribution in energy within the charge-storage silicon nitride. Simulated retention characteristics are compared with experiment results measured on SONOS devices with a gate dielectric stack consisting of a 1.8 nm tunnel oxide, a 10 nm oxynitride and a 4.5 nm blocking oxide. We obtain good agreement between simulations and measurements for temperatures from 22 to 225 °C. We also extract the trap distribution in the nitride with this model. Finally, we discuss the influence of the gate dielectric properties (thickness, trap energy, etc.) and temperature on data retention of SONOS devices.

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