Digital background calibration of redundant split-flash ADC in 45nm CMOS

This paper presents a redundant flash ADC using a “Split-ADC” calibration structure and lookup-table-based correction. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed in the background in the digital domain. This 5.8 ENOB flash ADC is designed for a sampling rate of 1Gs/s in 45nm SOI CMOS.

[1]  Un-Ku Moon,et al.  A 6b stochastic flash analog-to-digital converter without calibration or reference ladder , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[2]  Denis C. Daly,et al.  A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy , 2009, IEEE Journal of Solid-State Circuits.

[3]  Michael C. W. Coln,et al.  “Split ADC” Calibration for All-Digital Correction of Time-Interleaved ADC Errors , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Un-Ku Moon,et al.  "Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC , 2006, IEEE Journal of Solid-State Circuits.

[5]  M. P. Flynn,et al.  A 'digital' 6-bit ADC in 0.25 /spl mu/m CMOS , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[6]  M. P. Flynn,et al.  Digital calibration incorporating redundancy of flash ADCs , 2003, IEEE Trans. Circuits Syst. II Express Briefs.