A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer

Recently reported continuous-time (CT) ΔΣ modulators with opamp bandwidth compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially significant. For example, the quantizer in [2] accounts for 2.8mW of 8.5mW total power dissipation. Also, the input capacitance of multibit quantizers and the output parasitics of excess loop delay (ELD) compensation DACs result in increased power demand for summing circuits. To minimize power dissipation, two recent works use 1b quantizers with FIR DACs and replace ELD compensation DACs with a DAC followed by analog filter [3] or with feedback to the pre-amplifier [4]. ELD compensation may also be realized using digital logic following the quantizer [5]. This paper presents a low-power solution based on a highly digital multibit quantizer with embedded feedback to compensate for finite opamp bandwidth along with ELD. The quantizer consumes less than 10% of the total power and simplifies the analog circuits into a single DAC plus a feedforward loop filter with relaxed opamp requirements. Digital correction at the modulator output suggested by early work [6] is employed to shape DAC mismatch with the inherent noise transfer function (NTF) and to further relax circuit constraints. These digitally assisted techniques enable a CT ΔΣ modulator to achieve an FoM below 28fJ/conv-step.

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[2]  P. Fontaine,et al.  A low-noise low-voltage CT /spl Delta//spl Sigma/ modulator with digital compensation of excess loop delay , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[3]  Patrick Satarzadeh,et al.  A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[4]  Yun-Shiang Shu.  A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[5]  John G. Kauffman,et al.  A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW , 2012, 2012 IEEE International Solid-State Circuits Conference.

[6]  Shanthi Pavan,et al.  A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[7]  Koji Obata,et al.  A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[8]  John G. Kauffman,et al.  A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW , 2014, IEEE Journal of Solid-State Circuits.