The effect of reconfigurable units in superscalar processors

This paper describes OneChip, a third generation reconfigurable processor architecture that integrates a Reconfigurable Functional Unit (RFU) into a superscalar Reduced Instruction Set Computer (RISC) processor's pipeline. The architecture allows dynamic scheduling and dynamic reconfiguration. It also provides support for pre-loading configurations and for Least Recently Used (LRU) configuration management. To evaluate the performance of the OneChip architecture, several off-the-shelf software applications were compiled and executed on Sim-OneChip, an architecture simulator for OneChip that includes a software environment for programming the system. The architecture is compared to a similar one but without dynamic scheduling and without an RFU. OneChip achieves a performance improvement and shows a speedup range from 2.16 up to 32 for the different applications and data sizes used. The results show that dynamic scheduling helps performance the most on average, and that the RFU will always improve performance the best when most of the execution is in the RFU.

[1]  Abraham Silberschatz,et al.  Operating System Concepts , 1983 .

[2]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[3]  John Wawrzynek,et al.  The Garp Architecture and C Compiler , 2000, Computer.

[4]  Jeffrey A. Jacob.  Memory interfacing for the OneChip reconfigurable processor , 1998 .

[5]  David A. Patterson,et al.  Computer architecture (2nd ed.): a quantitative approach , 1996 .

[6]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.

[7]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[8]  Kunle Olukotun,et al.  A quantitative analysis of reconfigurable coprocessors for multimedia applications , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[9]  Paul Chow,et al.  Memory interfacing and instruction specification for reconfigurable processors , 1999, FPGA '99.

[10]  Maya Gokhale,et al.  The NAPA adaptive processing architecture , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[11]  Jorge Ernesto,et al.  Evaluation of the OneChip reconfigurable processor , 2000 .

[12]  Sarita V. Adve,et al.  RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors , 1997 .

[13]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[14]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[15]  Milos D. Ercegovac,et al.  FPGA-based structures for on-line FFT and DCT , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[16]  Scott Hauck,et al.  Configuration prefetch for single context reconfigurable coprocessors , 1998, FPGA '98.

[17]  André DeHon,et al.  DPGA-coupled microprocessors: commodity ICs for the early 21st Century , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[18]  Zhiyuan Li,et al.  Configuration compression for the Xilinx XC6200 FPGA , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[19]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[20]  Xinan Tang,et al.  A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors , 2000, FPL.

[21]  Fadi J. Kurdahi,et al.  The MorphoSys Parallel Reconfigurable System , 1999, Euro-Par.

[22]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .