Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Si single-electron transistors with sidewall depletion gates on a silicon-on-insulator nanowire are proposed and fabricated, using the combination of conventional lithography and process technology. The size dependence of device characteristics shows good controllability and reproducibility, and a dynamic multi-functional SET logic is successfully demonstrated at 10 K, for the first time.

[1]  Yasuo Takahashi,et al.  Fabrication technique for Si single-electron transistor operating at room temperature , 1995 .

[2]  John R. Tucker,et al.  Complementary digital logic based on the ``Coulomb blockade'' , 1992 .

[3]  Ken Uchida,et al.  A new design scheme for logic circuits with single electron transistors , 1999 .

[4]  H. Namatsu,et al.  Si complementary single-electron inverter , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[5]  Yasunobu Nakamura,et al.  Room-temperature Al single-electron transistor made by electron-beam lithography , 2000 .

[6]  Eun Kyu Kim,et al.  Fabrication and room-temperature characterization of a silicon self-assembled quantum-dot transistor , 1998 .

[7]  Ken Uchida,et al.  Room-temperature operation of multifunctional single-electron transistor logic , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[8]  S. Chou,et al.  Room temperature silicon single-electron quantum-dot transistor switch , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[9]  Ken Uchida,et al.  Challenge and prospects for silicon SET/FET hybrid circuits , 1999 .

[10]  Y. Takahashi,et al.  A multi-gate single-electron transistor and its application to an exclusive-OR gate , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[11]  Kazuhiko Matsumoto,et al.  Single-electron charging effects in Nb/Nb oxide-based single-electron transistors at room temperature , 1998 .

[12]  H. Matsuoka,et al.  Coulomb blockade in the inversion layer of a Si metal‐oxide‐semiconductor field‐effect transistor with a dual‐gate structure , 1994 .

[13]  Yasuo Takahashi,et al.  Fabrication method for IC-oriented Si single-electron transistors , 2000 .

[14]  Byung-Gook Park,et al.  Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling , 2000 .

[15]  G. Guegan,et al.  Coulomb blockade in low-mobility nanometer size Si MOSFET’s , 2000 .

[16]  Toshiro Hiramoto,et al.  Quantum mechanical effects in the silicon quantum dot in a single-electron transistor , 1997 .

[17]  H. Hasegawa,et al.  Voltage Gain in GaAs-Based Lateral Single-Electron Transistors Having Schottky Wrap Gates , 1999 .

[18]  R. A. Smith,et al.  Gate controlled Coulomb blockade effects in the conduction of a silicon quantum wire , 1997 .

[19]  Yasuo Takahashi,et al.  Size dependence of the characteristics of Si single-electron transistors on SIMOX substrates , 1996 .