A New Fabrication and Assembly Process for Ultrathin Chips

A new ultrathin chip fabrication and assembly process, consisting of a preprocess module Chipfilm and a postprocess module Pick, Crack, and Place, is presented. In contrast to the established wafer thinning technique, the preprocessed wafer substrates are prepared with extremely narrow buried cavities beneath the chip areas at a well-defined distance from the wafer surface, thus precisely defining the chip thickness a priori. After CMOS integration on those dedicated wafer substrates, chips are detached from the wafer surface by etching trenches at the chip edges into the buried cavities and breaking of residual anchors by mechanical force in the postprocess. The feasibility of the new process is demonstrated through a mixed-signal circuit having 38 000 digital and 2700 analog transistors, showing full functionality within specifications for 20-mum-thin chips even under a bending stress of up to 110 MPa.

[1]  Stefan Finkbeiner,et al.  Monocrystalline Si membranes for pressure sensors fabricated by a novel surface micromachining process using porous silicon , 2003, SPIE MOEMS-MEMS.

[2]  R. Ruther,et al.  A novel micromachining process for the fabrication of monocrystalline Si-membranes using porous silicon , 2003, TRANSDUCERS '03. 12th International Conference on Solid-State Sensors, Actuators and Microsystems. Digest of Technical Papers (Cat. No.03TH8664).

[3]  Cheong Yew Wee,et al.  Study of interaction between the function of grit size and residual damage of an ultra thin wafer , 2002, ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575).

[4]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[5]  T. Yonehara,et al.  ELTRAN ® ; Novel SOI Wafer Technology ELTRAN ® ; Novel SOI Wafer Technology , 2001 .

[6]  Khalil Najafi,et al.  A CMOS Dissolved Wafer Process For Integrated P++ Microelectromechanical Systems , 1995, Proceedings of the International Solid-State Sensors and Actuators Conference - TRANSDUCERS '95.

[7]  Payman Zarkesh-Ha,et al.  Interconnect opportunities for gigascale integration , 2002, IBM J. Res. Dev..

[8]  Karlheinz Bock,et al.  Polymer Electronics Systems - Polytronics , 2005, Proceedings of the IEEE.

[9]  S. Takyu,et al.  A study on chip thinning process for ultra thin memory devices , 2008, 2008 58th Electronic Components and Technology Conference.

[10]  Ulrich Ramacher,et al.  3D chip stack technology using through-chip interconnects , 2005, IEEE Design & Test of Computers.

[11]  C. Burwick,et al.  A Seamless Ultra-Thin Chip Fabrication and Assembly Process , 2006, 2006 International Electron Devices Meeting.

[12]  K. Bock,et al.  The challenge of ultra thin chip assembly , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[13]  Ralf B. Bergmann,et al.  Quasi-monocrystalline silicon for thin-film devices , 1999 .

[14]  Pasqualina M. Sarro,et al.  Substrate options and add-on process modules for monolithic RF silicon technology , 2002, Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting.

[15]  M. Koyanagi,et al.  Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections , 2006, IEEE Transactions on Electron Devices.

[16]  W. Kroninger,et al.  Thinning and singulation of silicon: root causes of the damage in thin chips , 2006, 56th Electronic Components and Technology Conference 2006.

[17]  Martin Zimmermann,et al.  Ultra-Thin Chips on Foil for Flexible Electronics , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[18]  E. Beyne,et al.  3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias , 2006, 2006 International Electron Devices Meeting.

[19]  H. Reichl,et al.  Ultra thin chips for miniaturized products , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[20]  C. Van Hoof,et al.  Influence of Extreme Thinning on 130-nm Standard CMOS Devices for 3-D Integration , 2008, IEEE Electron Device Letters.

[21]  M. Schubert,et al.  150-mm layer transfer for monocrystalline silicon solar cells , 2006 .

[22]  Ronald Dekker,et al.  Substrate transfer for RF technologies , 2003 .

[23]  R. Brendel,et al.  Structural changes in porous silicon during annealing , 2003 .