Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection

Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology.

[1]  Shohaib Aboobacker.  RAZOR: circuit-level correction of timing errors for low-power operation , 2011 .

[2]  Erwan Nogues,et al.  Algorithmic-Level Approximate Computing Applied to Energy Efficient HEVC Decoding , 2019, IEEE Transactions on Emerging Topics in Computing.

[3]  Massimo Alioto.  Ultra-low power design approaches for IoT , 2014, 2014 IEEE Hot Chips 26 Symposium (HCS).

[4]  Naresh R. Shanbhag,et al.  Energy-efficient signal processing via algorithmic noise-tolerance , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[5]  David M. Bull,et al.  RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[6]  N.R. Shanbhag,et al.  Reduced precision redundancy for low-power digital filtering , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[7]  Jun Zhou,et al.  Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling , 2018, Integr..

[8]  Ilia Polian,et al.  Adaptive voltage over-scaling for resilient applications , 2011, 2011 Design, Automation & Test in Europe.

[9]  Trevor Mudge,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, VLSIC 2005.

[10]  John Sartori,et al.  Slack redistribution for graceful degradation under voltage overscaling , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[11]  Massoud Pedram,et al.  Dynamic voltage and frequency scaling based on workload decomposition , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[12]  Sherali Zeadally,et al.  A survey and taxonomy on energy efficient resource allocation techniques for cloud computing systems , 2016, Computing.

[13]  David Blaauw,et al.  Opportunities and challenges for better than worst-case design , 2005, ASP-DAC.

[14]  K.A. Bowman,et al.  Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[15]  Lee Gillam,et al.  Energy efficient computing, clusters, grids and clouds: A taxonomy and survey , 2017, Sustain. Comput. Informatics Syst..

[16]  Yiorgos Tsiatouhas,et al.  Timing error tolerance in nanometer ICs , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[17]  Haranath Kar,et al.  Multi-threshold CMOS design for low power digital circuits , 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

[18]  Massimo Alioto,et al.  Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[19]  Luca Benini,et al.  Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology , 2007, GLSVLSI '07.

[20]  L. Benini,et al.  Battery-driven dynamic power management of portable systems , 2000, Proceedings 13th International Symposium on System Synthesis.

[21]  Kaushik Roy,et al.  Analysis and characterization of inherent application resilience for approximate computing , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[22]  Roberto Giorgio Rizzo,et al.  Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling , 2017, 2017 New Generation of CAS (NGCAS).

[23]  Luca Benini,et al.  A variation tolerant architecture for ultra low power multi-processor cluster , 2013, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

[24]  Naresh R. Shanbhag,et al.  Reliable low-power digital signal processing via reduced precision redundancy , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[26]  Jun Zhou,et al.  Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS , 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[27]  Naresh R. Shanbhag,et al.  A low-power digital filter IC via soft DSP , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[28]  Diana Marculescu,et al.  Analysis of dynamic voltage/frequency scaling in chip-multiprocessors , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[29]  Trevor Mudge,et al.  Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.

[30]  Kaushik Roy,et al.  CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Massimo Alioto,et al.  Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping , 2016, VLSI-SoC.

[32]  Mingoo Seok,et al.  Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique , 2015, IEEE Journal of Solid-State Circuits.