An architectural design for parallel fractal compression

Fractal image compression has many features that makes it a powerful compression scheme, but it has been mainly restricted to archival storage due to its time consuming encoding algorithm. In this paper, we take a known quad-tree fractal encoding algorithm and design an ASIC parallel image processing array that can encode reasonably sized gray-scale images in real-time. In designing this architecture, we include novel optimizations that result in speed improvements at the algorithmic, architectural, and circuit levels.

[1]  Yuval Fisher.  Fractal Image Compression , 1994 .

[2]  D. J. Jackson,et al.  A parallel fractal image compression algorithm for hypercube multiprocessors , 1995, Proceedings of the Twenty-Seventh Southeastern Symposium on System Theory.

[3]  Michael F. Barnsley,et al.  Fractals everywhere , 1988 .

[4]  Edward W. Davis,et al.  A bit-serial VLSI array processing chip for image processing , 1990 .

[5]  Sang Uk Lee,et al.  Novel fractal image compression method with non-iterative decoder , 1995, Proceedings., International Conference on Image Processing.

[6]  Arnaud E. Jacquin,et al.  Application Of Recurrent Iterated Function Systems To Images , 1988, Other Conferences.

[7]  John Kominek.  Algorithm for fast fractal image compression , 1995, Electronic Imaging.

[8]  Israel Koren.  Computer arithmetic algorithms , 1993 .

[9]  Paolo Ienne,et al.  Bit-Serial Multipliers and Squarers , 1994, IEEE Trans. Computers.

[10]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[11]  Richard F. Lyon,et al.  Two's Complement Pipeline Multipliers , 1976, IEEE Trans. Commun..