System-in-Package (SiP)

System-in-package (SiP) technology has been used extensively on consumer products such as smartwatches, smartphones, tablets, notebooks, TWS (true wireless stereo), etc. The key assembly processes of SiP technology are basically SMT (surface mount technology) and flip chip technology, which will be presented and discussed in this chapter. The difference between the SoC (system-on-chip) and SiP, the intention and actual applications of SiP, and some examples in using SiP technology to manufacture consumer products will be briefly mentioned first.

[1]  Saptadeep Pal,et al.  Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[2]  B. Banijamali,et al.  Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[3]  C. Wong,et al.  Characterization of a no-flow underfill encapsulant during the solder reflow process , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).

[5]  Kuo-Shu Kao,et al.  Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[6]  Andy Heinig,et al.  Heterogeneous Interposer Based Integration of Chips with Copper Pillars and C4 Balls to Achieve High Speed Interfaces for ADC Application , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[7]  F. Fournel,et al.  Innovative wafer-level encapsulation & underfill material for silicon interposer application , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[8]  Shin-Puu Jeng,et al.  3D Heterogeneous Integration with Multiple Stacking Fan-Out Package , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[9]  Shin-Puu Jeng,et al.  Reliability evaluation of a CoWoS-enabled 3D IC package , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[10]  John H Lau,et al.  Fan-out wafer-level packaging for 3D IC heterogeneous integration , 2018, 2018 China Semiconductor Technology International Conference (CSTIC).

[11]  M. Kao,et al.  Through-Silicon Hole Interposers for 3-D IC Integration , 2014, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[12]  Xiaowu Zhang,et al.  Development of 3-D Silicon Module With TSV for System in Packaging , 2010, IEEE Transactions on Components and Packaging Technologies.

[13]  Ji-Jan Chen,et al.  Unified methodology for heterogeneous integration with CoWoS technology , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[14]  Andrej Kolbasow,et al.  Laser-assisted bonding (LAB) and de-bonding (LAdB) as an advanced process solution for selective repair of 3D and multi-die chip packages , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[15]  Jing Li,et al.  Wafer Scale Flexible Interconnect Transfer for Hetrogeneous Integration , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[16]  Amram Eitan,et al.  Thermo-Compression Bonding for fine-pitch copper-pillar flip-chip interconnect - tool features as enablers of unique technology , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[17]  Sheng-Tsai Wu,et al.  Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW) , 2011 .

[18]  J. Lau,et al.  Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[19]  S. Voges,et al.  Non-Destructive Testing for System-in-Package Integrity Analysis , 2017 .

[20]  Dan Oh,et al.  Low Cost Si-Less RDL Interposer Package for High Performance Computing Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[21]  Curtis Zwenger,et al.  Heterogeneous Integration Using Organic Interposer Technology , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[22]  N. Lee,et al.  Assembly and Reliability of Lead-Free Solder Joints , 2020 .

[23]  John H. Lau,et al.  3D IC Heterogeneous Integration by FOWLP , 2018 .

[24]  R. Chaware,et al.  Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[25]  Youngtak Lee,et al.  Practical Application and Analysis of Lead-Free Solder on Chip-On-Flip-Chip SiP for Hearing Aids , 2017 .

[26]  C. Chang,et al.  Effects of underfill encapsulant on the mechanical and electrical performance of a functional flip chip device , 1997, Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268).

[27]  J. H. Lau,et al.  Taguchi design of experiment for wafer bumping by stencil printing , 2000, ECTC 2000.

[28]  Eric Ouyang,et al.  Warpage and Void Simulation of System in Package , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[29]  Yu-Sheng Hsieh,et al.  3D heterogeneous integration structure based on 40 nm- and 0.18 µm-technology nodes , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[30]  J. Lau,et al.  Characteristics and Reliability of No-Flow Underfills for Solder Bumped Flip Chip Assemblies , 1999 .

[31]  Nick Renaud-Bezot Size Matters – Embedding as an Enabler of Next-Generation SiPs , 2013 .

[32]  John H. Lau,et al.  Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration system-in-package (SiP) , 2012, Microelectron. Reliab..

[33]  Robert N. Dean,et al.  Using SPICE to Model Nonlinearities Resulting from Heterogeneous Integration of Complex Systems , 2017 .

[34]  J. Chen,et al.  Design, Fabrication and Characterization of TSV Interposer Integrated 3D Capacitor for SIP Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[35]  C.P. Wong,et al.  Recent advances in flip-chip underfill: materials, process, and reliability , 2004, IEEE Transactions on Advanced Packaging.

[37]  R. Mahajan,et al.  Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[38]  J. H. Lau,et al.  Failure analysis of solder bumped flip chip on low-cost substrates , 2000 .

[39]  Sheng-Tsai Wu,et al.  Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[40]  J. H. Lau,et al.  Fracture Mechanics Analysis of Low Cost Solder Bumped Flip Chip Assemblies With Imperfect Underfills , 2000 .

[41]  J. Lau,et al.  Stencil printing of underfill for flip chips on organic-panel and Si-wafer assemblies , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[42]  Vinayak Pandey,et al.  Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology , 2017 .

[43]  J. H. Lan,et al.  Characterization of underfill materials for functional solder bumped flip chips on board applications , 1999 .

[45]  Mohan Nagar,et al.  Ultra large System-in-Package (SiP) module and novel packaging solution for networking applications , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[46]  Koichi Tanaka,et al.  Development of Thinner POP Base Package by Die Embedded and RDL Structure , 2017 .

[47]  Robert S. Schwartz,et al.  Solid Logic Technology: Versatile, high-performance microelectronics , 1964, IBM J. Res. Dev..

[48]  Madhavan Swaminathan,et al.  Heterogeneous Integration of 5G and Millimeter-Wave Diplexers with 3D Glass Substrates , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[49]  N. Pesika,et al.  Time, temperature, and mechanical fatigue dependence on underfill adhesion , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[50]  Yu-Min Lin,et al.  An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[51]  J. Lau,et al.  Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates , 2002 .

[53]  Doug Mitchell,et al.  3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency , 2013 .

[54]  Y. C. Kim,et al.  Molded underfill (MUF) technology for flip chip packages in mobile applications , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[55]  J. Lau,et al.  Fan-Out Wafer-Level Packaging for Heterogeneous Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[56]  John H. Lau,et al.  Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.

[57]  Douglas Yu,et al.  InFO_SoW (System-on-Wafer) for High Performance Computing , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[58]  Bob Chylak,et al.  Wire Bonding Looping Solutions for High Density System-in-Package (SiP) , 2017 .

[59]  J. H. Lau,et al.  Effects of underfill delamination and chip size on the reliability of solder bumped Flip Chip on board , 1999 .

[60]  Pouya Talebbeydokhti,et al.  Ultra Large Area SIPs and Integrated mmW Antenna Array Module for 5G mmWave Outdoor Applications , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[61]  Kevin Gaffney,et al.  Transfer molding encapsulation of flip chip array packages , 2000 .

[62]  Seung Wook Yoon,et al.  Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[63]  Dale Ibbotson,et al.  Enabling the 2.5D Integration , 2012 .

[64]  B. Wun,et al.  Characterisation and Evaluation of the Underfill Encapsulants for Flip Chip Assembly , 1995 .

[65]  Albert Lan,et al.  Alternative 3D Small form Factor Methodology of System in Package for IoT and Wearable Devices Application , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[66]  A. Hanna,et al.  Extremely Flexible (1mm Bending Radius) Biocompatible Heterogeneous Fan-Out Wafer-Level Platform with the Lowest Reported Die-Shift (<6 µm) and Reliable Flexible Cu-Based Interconnects , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[67]  Basil Milton,et al.  Smart Wire Bond Solutions for SiP and Memory Packages , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[68]  Stephan Borel,et al.  A Novel Structure for Backside Protection Against Physical Attacks on Secure Chips or SiP , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[69]  Kilsoo Kim,et al.  Study of Advanced Fan-Out Packages for Mobile Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[70]  Yuan Xie,et al.  Cost-effective design of scalable high-performance systems using active and passive interposers , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[71]  John H. Lau,et al.  Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates , 2010 .

[72]  S. Jeng,et al.  Hybrid Fan-out Package for Vertical Heterogeneous Integration , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[73]  J. H. Lau,et al.  Effects of underfill material properties on the reliability of solder bumped flip chip on board with imperfect underfill encapsulants , 2000 .

[74]  Jie Chen,et al.  System Co-design of a 600V GaN FET Power Stage with Integrated Driver in a QFN System-in-Package (QFN-SiP) , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[75]  Frank D. Egitto,et al.  3D Integration of System-in-Package (SiP) Using Organic In terposer: Toward SiP-Interposer-SiP for High-End Electronics , 2013 .

[76]  D. Danovitch,et al.  Controlling Underfill Lateral Flow to Improve Component Density in Heterogeneously Integrated Packaging Systems , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[77]  Curtis Zwenger,et al.  Chip Stackable, Ultra-thin, High-Flexibility 3D FOWLP (3D SWIFT® Technology) for Hetero-Integrated Advanced 3D WL-SiP , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[78]  John H. Lau,et al.  Process integration of 3D Si interposer with double-sided active chip attachments , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[79]  John H. Lau,et al.  SMT COMPATIBLE NO-FLOW UNDERFILL FOR SOLDER BUMPED FLIP CHIP ON LOW-COST SUBSTRATES , 1998 .

[80]  J. H. Lau,et al.  Shock and Vibration of Solder Bumped Flip Chip on Organic Coated Copper Boards , 1996 .

[81]  Seung Wook Yoon,et al.  Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[82]  J. H. Lau,et al.  How to select underfill materials for solder bumped flip chips on low cost substrates , 1998 .

[83]  Gabriel Pares,et al.  Flip chip reliability and design rules for SIP module , 2017 .

[84]  J. Lau,et al.  Thermal management of 3D IC integration with TSV (through silicon via) , 2009, 2009 59th Electronic Components and Technology Conference.

[85]  Mohan Nagar,et al.  3D SiP with Organic Interposer for ASIC and Memory Integration , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[86]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[87]  J. Lau,et al.  Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Substrates , 2015, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[88]  Yu-Po Wang,et al.  EMI Shielding Technology in 5G RF System in Package Module , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[89]  Clark Hu,et al.  Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology , 2017, IEEE Transactions on Electron Devices.

[90]  John H. Lau Patent Issues of Fan-Out Wafer-Level Packaging , 2018 .

[91]  Pascal Couderc,et al.  Stacking of known good rebuilt wafers for high performance memory and SiP , 2013 .

[92]  F. X. Che,et al.  Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI) , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[93]  Cheng-Chih Chen,et al.  Moisture Effect on Physical Failure of Plastic Molded SiP Module , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[94]  J. Lau,et al.  A high throughput and reliable thermal compression bonding process for advanced interconnections , 2015, Electronic Components and Technology Conference.

[95]  Yong Liu,et al.  Modeling for reliability of ultra thin chips in a system in package , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[96]  Pouya Talebbeydokhti,et al.  A Zero Height Small Size Low Cost RF Interconnect Substrate Technology For RF Front Ends For M.2 Modules And SiP , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[97]  J. Lau,et al.  Experimental and Analytical Studies of Encapsulated Flip Chip Solder Bumps on Surface Laminar Circuit Boards , 1993 .

[98]  Sheng-Tsai Wu,et al.  Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV) , 2011 .

[99]  Chi-Wei Wang,et al.  A Novel Warpage Reinforcement Architecture with RDL Interposer for Heterogeneous Integrated Packages , 2020, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC).

[100]  Tai Chong Chai,et al.  Development of Large Die Fine-Pitch Cu/Low- $k$ FCBGA Package With Through Silicon via (TSV) Interposer , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[101]  Madhavan Swaminathan,et al.  A System-in-Package Based Energy Harvesting for IoT Devices with Integrated Voltage Regulators and Embedded Inductors , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[102]  John Knickerbocker,et al.  Heterogeneous Integration Technology Demonstrations for Future Healthcare, IoT, and AI Computing Solutions , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[103]  Kilsoo Kim,et al.  Advanced Fan-Out Package SI/PI/Thermal Performance Analysis of Novel RDL Packages , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[104]  S.B. Park,et al.  Design Guideline of 2.5D Package with Emphasis on Warpage Control and Thermal Management , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[105]  Chin-Li Kao,et al.  Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[107]  Jinglin Shi,et al.  High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP) , 2010, IEEE Transactions on Advanced Packaging.

[108]  Eric Beyne,et al.  A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-µm Pitch , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[109]  Xin Sun,et al.  Modeling and Design of a 3D Interconnect Based Circuit Cell Formed with 3D SiP Techniques Mimicking Brain Neurons for Neuromorphic Computing Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[110]  John H. Lau,et al.  Fan-Out Wafer-Level Packaging , 2018 .

[111]  C. Selvanayagam,et al.  Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps , 2009, IEEE Transactions on Advanced Packaging.

[112]  Heng-Chieh Chien,et al.  Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[113]  Eric He,et al.  Innovative Packaging Solutions of 3D Double Side Molding with System in Package for IoT and 5G Application , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).

[114]  Chueh-An Hsieh,et al.  Fan-out technologies for WiFi SiP module packaging and electrical performance simulation , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[115]  John H. Lau,et al.  Recent Advances and New Trends in Flip Chip Technology , 2016 .

[116]  John H. Lau,et al.  TSV manufacturing yield and hidden costs for 3D IC integration , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[117]  Hugo Gamboa,et al.  Heterogeneous Integration Challenges Within Wafer Level Fan-Out SiP for Wearables and IoT , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

[118]  Hongbin Yu,et al.  Integration of magnetic materials into package RF and power inductors on organic substrates for system in package (SiP) applications , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[119]  M. Brillhart,et al.  Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[120]  K. Lang,et al.  Chip embedding technology developments leading to the emergence of miniaturized system-in-packages , 2010, 18th European Microelectronics & Packaging Conference.

[121]  Frank D. Egitto,et al.  3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics , 2013 .

[122]  J. Lau,et al.  Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications , 2000, Packaging of Electronic and Photonic Devices.

[123]  P. A. Totta,et al.  SLT device metallurgy and its monolithic extension , 1969 .