论文信息 - Memory Barriers: a Hardware View for Software Hackers

Memory Barriers: a Hardware View for Software Hackers

So what possessed CPU designers to cause them to inflict memory barriers on poor unsuspecting SMP software designers? In short, because reordering memory references allows much better performance, and so memory barriers are needed to force ordering in things like synchronization primitives whose correct operation depends on ordered memory references. Getting a more detailed answer to this question requires a good understanding of how CPU caches work, and especially what is required to make caches really work well. The following sections:

Paul E. McKenney | Ibm Beaverton | P. McKenney | Ibm Beaverton

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