Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters
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[1] M.-C. Shiau,et al. The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters , 1990 .
[2] Mark Horowitz,et al. Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Lance A. Glasser,et al. The Analog Behavior of Digital Integrated Circuits , 1981, 18th Design Automation Conference.
[4] Mohamed I. Elmasry. Interconnection delays in MOSFET VLSI , 1981 .
[5] E. Polak. Introduction to linear and nonlinear programming , 1973 .
[6] R. J. Antinone,et al. The modeling of resistive interconnects for integrated circuits , 1983 .
[7] Lance A. Glasser,et al. Delay and Power Optimization in VLSI Circuits , 1984, 21st Design Automation Conference Proceedings.
[8] M.D. Matson,et al. Macromodeling and Optimization of Digital MOS VLSI Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Andrei Vladimirescu,et al. The Simulation of MOS Integrated Circuits Using SPICE2 , 1980 .
[10] T. Sakurai,et al. Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.
[11] Jr. J. Wyatt. Monotone sensitivity of nonlinear uniform RC transmission lines, with application to timing analysis of digital MOS integrated circuits , 1985 .
[12] Carver A. Mead,et al. Minimum propagation delays in VLSI , 1982 .
[13] K.C. Saraswat,et al. Effect of scaling of interconnections on the time delay of VLSI circuits , 1982, IEEE Transactions on Electron Devices.
[14] Chung-Yu Wu,et al. A new autosizing algorithm for CMOS combinational logic circuits , 1989, International Symposium on VLSI Technology, Systems and Applications,.
[15] J.D. Meindl,et al. Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.
[16] Carver Mead,et al. Signal Delay in General RC Networks , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] Kjell O. Jeppson,et al. CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[18] Chung-Yu Wu,et al. An Efficient Timing Model for CMOS Combinational Logic Gates , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[19] Chung-Yu Wu,et al. Physical timing models of small-geometry CMOS inverters and multi-input NAND/NOR gates and their applications , 1989 .
[20] Jeremy C. Wyatt. Signal delay in rc mesh networks , 1985 .
[21] Chung-Yu Wu,et al. A new interconnection delay model considering the effects of short-channel logic gates , 1988, 1988., IEEE International Symposium on Circuits and Systems.