The interdependence between delay-optimization of synthesized networks and testing

As CAD tools become more sophisticated, they can synthesize logic networks that more nearly optimize the circuit area resources to maximize operating speeds. In this work we show, through formal arguments, that the path delays in such optimized networks will follow a more compact distribution and, in the extreme in some networks, will all be equal to the maximum delay through the network (cycle time). The impact of this type of synthesized network on delay testing will be shown and compared to the case for nonoptimized designs. Finally, recommendations will be made on how network timing optimization can be done in such a way as to minimize the adverse impact on product yield.