Improved XFBT: A Low-Power Topology of Network-on-Chip

The article discusses the issues related to the on-chip network topology, analyzes the XBFT topology, improves its structure in power consumption. Authors designed a simulation program that by analyzing the topology routing hops to roughly determine the power consumption of routing topology and for the preparation of modified XBFT roughly determine the topology of the routing topology by analyzing the power consumption topology routing hops the simulation program, Finally, the results from the running of 6 simulation program that extracted and these results were analyzed. The result shows that the improved topology saved about 20% of the number of routing hops.