A function reuse based scan chain structure for error tolerance

Since the soft error has become the predominant cause of chip failures,a high reliable BIST structure called TMR-CBILBO is proposed in this paper for soft error tolerance.By constructing triple modular redundant scan chain structure and inserting voting circuit at the trigger output,TMR-CBILBO can effectively prevent the single event upset and tolerate the soft error caused by transient failures.Based on the function reuse of multiple input signature register(MISR),TMR-CBILBO effectively reduces the area overhead of error tolerance design.TMR-CBILBO is implemented with UMC 0.18 μm process according to ISCAS 89 reference circuit.The experiment results show that the soft error reduction rate is ranging from 95.56% to 98.21%,area overhead is ranging from 71.68% to 84.21%,and performance overhead is ranging from 1.75% to 4.39%.