Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM

A compact quaternary cell circuit using a single MOS transistor and two magnetic tunnel junction devices (1T-2MTJ) is proposed for a high-density nonvolatile bit-serial content-addressable memory (CAM). The use of quaternary CAM-cell structure makes the search-cycle counts half, which achieves a high-speed search operation. Moreover, the power supply of a CAM word circuit is cut off whenever a mismatched cell is detected during search operation, which greatly reduces the static power dissipation. In fact, the average activation ratio of a 128-bit CAM word circuit is about 2.05 percent. The efficiency of the proposed CAM-cell structure is discussed in comparison with a conventional binary CAM-cell structure under a 0.14 um CMOS/MTJ technology.

[1]  J. Lin,et al.  An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique , 2002, IEEE J. Solid State Circuits.

[2]  Shoji Ikeda,et al.  Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices , 2009 .

[3]  Manoj Sachdev,et al.  Low-Leakage Storage Cells for Ternary Content Addressable Memories , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  H. Ohno,et al.  Magnetic Tunnel Junctions for Spintronic Memories and Beyond , 2007, IEEE Transactions on Electron Devices.

[5]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.

[6]  H. Ohno,et al.  A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction. , 2010, Nature materials.

[7]  James B. Kuo,et al.  A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell , 2001 .

[8]  Takahiro Hanyu,et al.  TMR-Based Logic-in-Memory Circuit for Low-Power VLSI , 2004, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[9]  H. Ohno,et al.  Current-Induced Magnetization Switching in MgO Barrier Magnetic Tunnel Junctions With CoFeB-Based Synthetic Ferrimagnetic Free Layers , 2008, IEEE Transactions on Magnetics.

[10]  T. Ogura,et al.  A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing , 2000, IEEE Journal of Solid-State Circuits.

[11]  H. Ohno,et al.  Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions , 2008 .

[12]  James B. Kuo,et al.  A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme , 2002 .

[14]  Yen-Jen Chang.  90 nm TCAM cell design with leakage suppression technique , 2009 .