Optimized Hardware Crypto Engines for XTEA and SHA-512 for Wireless Sensor Nodes

Objectives: This study proposes an optimized power-efficient cryptosystem that is suitable for Wireless Sensor Networks. Methods: A number of cryptographic algorithms have been proposed to secure Wireless Sensor Networks. However, these compute-intensive and power-hungry algorithms do not take into consideration the limitations of resource found on the sensor nodes. We propose profiling some of these popular algorithms to identify the speed bottlenecks and develop hardware accelerators that maintain the real-time performance, with an efficient use of power. Findings: The proposed optimizations to the hardware accelerators were mapped to reconfigurable computing devices. Results show that the performance of the proposed hardware outperforms the software implementation running on contemporary CPU by up to 21.9×. In addition, the results indicate that the hardware is efficiently managing its power budget. Application: These accelerators can be utilized in heterogeneous system architectures, where the CPU controls the overall operations, and the accelerators efficiently perform the necessary encryption and decryption.

[1]  Afaq Ahmad,et al.  On determination of LFSR structures to assure more reliable and secure designs of cryptographic systems , 2014, Proceedings of 3rd International Conference on Reliability, Infocom Technologies and Optimization.

[2]  Narayanan Vijaykrishnan,et al.  Accelerating neuromorphic vision algorithms for recognition , 2012, DAC Design Automation Conference 2012.

[3]  Jaroslaw Sugier,et al.  Organization of AES Cryptographic Unit for Low Cost FPGA Implementation , 2008, 2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX.

[4]  Yee Wei Law,et al.  How to Secure a Wireless Sensor Network , 2005, 2005 International Conference on Intelligent Sensors, Sensor Networks and Information Processing.

[5]  Armando Astarloa,et al.  Robustness Analysis of Different AES Implementations on SRAM Based FPGAs , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[6]  Björn Stelte.  Toward development of high secure sensor network nodes using an FPGA-based architecture , 2010, IWCMC.

[7]  Sayyid Samir Al-Busaidi,et al.  Computing and Listing of Number of Possible m-Sequence Generators of Order n , 2013 .

[8]  M.Y. Javed,et al.  A Performance Comparison of Data Encryption Algorithms , 2005, 2005 International Conference on Information and Communication Technologies.

[9]  Chi-Jeng Chang,et al.  The FPGA Implementation of 128-bits AES AlgorithmBased on Four 32-bits Parallel Operation , 2007, The First International Symposium on Data, Privacy, and E-Commerce (ISDPE 2007).

[10]  Ingrid Verbauwhede,et al.  A 21.54 Gbits/s fully pipelined AES processor on FPGA , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[11]  Ignacio Algredo-Badillo,et al.  Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm , 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

[12]  Anupam Joshi,et al.  Security for wireless sensor networks , 2004 .

[13]  Rommel García,et al.  A compact FPGA-based processor for the Secure Hash Algorithm SHA-256 , 2014, Comput. Electr. Eng..