A Hazard-Free Majority Voter for TMR-Based Fault Tolerance in Asynchronous Circuits
暂无分享,去创建一个
[1] Andreas G. Veneris,et al. Seamless Integration of SER in Rewiring-Based Design Space Exploration , 2006, 2006 IEEE International Test Conference.
[2] M. Nicolaidis,et al. Design for soft error mitigation , 2005, IEEE Transactions on Device and Materials Reliability.
[3] Régis Leveugle,et al. Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic , 2006, IEEE Transactions on Computers.
[4] Sujit Dey,et al. Separate dual-transistor registers: a circuit solution for on-line testing of transient error in UDMC-IC , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..
[5] Cecilia Metra,et al. Novel transient fault hardened static latch , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[6] Yiorgos Makris,et al. Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines , 2007, IEEE Transactions on Computers.
[7] Nur A. Touba,et al. Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[8] Alain J. Martin,et al. SEU-tolerant QDI circuits [quasi delay-insensitive asynchronous circuits] , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.
[9] Kartik Mohanram,et al. Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.