Semiconductor memory device having shared bit line sense amplifier scheme and driving method thereof

The present invention relates to, and more particularly a semiconductor memory device and a driving method thereof having a shared bit line sense amplifier structure to a semiconductor design technology. The present invention provides a semiconductor memory device and a driving method thereof having a shared bit line sense amplifier structure capable of preventing the floating of the non-selected bit line pair has the purpose. Further, an object of the present invention is to provide a semiconductor memory device having a shared bit line sense amplifier structure in which, while achieving the above object can minimize the increase in the chip area. The invention has been placed in the in implementing a semiconductor memory device having a shared bit line sense amplifier structure, the bit line pre-charge bit line portion separating portion outer side (on the cell array). Therefore, the bit line precharge portion is required for both the upper and lower cell array is necessary because the two bit line precharge portion for one of the bit line sense amplifier. In this case, it is possible to prevent the bit lines of non-selected cell array pair is floating. The present invention is a bit line precharge portion with a metal line for supplying a bit line precharge voltage (VBLP) in order to minimize the chip area is increased according to arranged at each end of only the bit line pre-order portion of the one side, the bit line pre-charge the other end of the bit line is a metal line for supplying a voltage (VBLP) does not exist pre-order branch is to propose a layout for feeding through the dummy bit line and the active region from the metal line. Shared bit line sense amplifier, the bit line equalizing signal, the bit line pre-charge voltage, the active regions, the dummy bit line