Fault-tolerance and noise modelling in nanoscale circuit design

Fault-tolerance in integrated circuit design has become an alarming issue for circuit designers and semiconductor industries wishing to downscale transistor dimensions to their utmost. The motivation to conduct research on fault-tolerant design is backed by the observation that the noise which was ineffective in the large-dimension circuits is expected to cause a significant downgraded performance in low-scaled transistor operation of future CMOS technology models. This paper is destined to give an overview of all the major fault-tolerance techniques and noise models proposed so far. Summing and analysing all this work, we have divided the literature into three categories and discussed their applicability in terms of proposing circuit design modifications, finding output error probability or methods proposed to achieve highly accurate simulation results.

[1]  John P. Hayes,et al.  Probabilistic transfer matrices in symbolic reliability analysis of logic circuits , 2008, TODE.

[2]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[3]  Jie Chen,et al.  A probabilistic-based design for nanoscale computation , 2004 .

[4]  R. Iris Bahar,et al.  A Model for Soft Errors in the Subthreshold CMOS Inverter , 2006 .

[5]  Sandeep K. Shukla,et al.  Fault‐ and Defect‐Tolerant Architectures for Nanocomputing , 2009 .

[6]  Hong Zhao,et al.  Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[7]  Massoud Pedram,et al.  Probabilistic error propagation in logic circuits using the Boolean difference calculus , 2008, 2008 IEEE International Conference on Computer Design.

[8]  Narinderjit Singh,et al.  Joint and marginal probability analyses of Markov Random Field networks for digital logic circuits , 2010, 2010 International Conference on Intelligent and Advanced Systems.

[9]  David J. Lilja,et al.  Guiding Circuit Level Fault-Tolerance Design with Statistical Methods , 2008, 2008 Design, Automation and Test in Europe.

[10]  Markov Random Field , 2010, Encyclopedia of Machine Learning.

[11]  Narinderjit Singh,et al.  Highly noise-tolerant design of digital logic gates using Markov Random Field modelling , 2010, 2010 2nd International Conference on Electronic Computer Technology.

[12]  Jianbo Gao,et al.  Faults, error bounds and reliability of nanoelectronic circuits , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

[13]  H. B. Mitchell.  Markov Random Fields , 1982 .

[14]  Sanjukta Bhanja,et al.  Probabilistic Error Modeling for Nano-Domain Logic Circuits , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  David J. Lilja,et al.  MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple Environments , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).