Simulation of yield/cost learning curves with Y4

This paper describes a prototype of a discrete event simulator-Y4 (yield forecaster)-capable of simulating defect related yield loss and manufacturing cost as a function of time, for a multiproduct IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The paper presents a set of models that take into account the effect of particles introduced during wafer processing as well as changes in their densities due to process improvements. These models also illustrate a possible way of accounting for the primary attributes of fabrication, product, and failure analysis which affect yield learning. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies.

[1]  P. Nag,et al.  Yield Learning Simulation , 1998 .

[2]  Wojciech Maly,et al.  From Contamination to Defects, Faults and Yield Loss , 1996 .

[3]  Robert W. Atherton,et al.  Wafer Fabrication: Factory Performance and Analysis , 1995 .

[4]  Wojciech Maly,et al.  Hierarchical extraction of critical area for shorts in very large ICs , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

[5]  Wojciech Maly,et al.  Cost of "ad hoc" wafer release policies , 1995, Proceedings of International Symposium on Semiconductor Manufacturing.

[6]  Roger E. Bohn.  The impact of process noise on VLSI process improvement , 1995 .

[7]  U. Kaempf,et al.  The binomial test: a simple tool to identify process problems , 1995 .

[8]  Duncan M. Walker,et al.  Hierarchical mapping of spot defects to catastrophic faults-design and applications , 1995 .

[9]  M. E. Thomas,et al.  Extraction of defect size distributions in an IC layer using test structure data , 1994 .

[10]  S.C.H. Lu,et al.  Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants , 1994 .

[11]  Wojciech Maly,et al.  Cost of Silicon Viewed from VLSI Design Perspective , 1994, 31st Design Automation Conference.

[12]  Wojciech Maly,et al.  Estimation of wafer cost for technology design , 1993, Proceedings of IEEE International Electron Devices Meeting.

[13]  N. Abt,et al.  Cost Analysis for a Multiple Product / Multiple Process Factory: Application of SEMATECH's Future Factory Design Methodology , 1993, Proceedings. IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop.

[14]  D. Dance,et al.  Using yield models to accelerate learning curve progress (semiconductor industry) , 1992 .

[15]  D. Dance,et al.  Using yield models to accelerate learning curve progress , 1990, IEEE/SEMI International Symposium on Semiconductor Manufacturing Science.

[16]  B. Tracy,et al.  Use of advanced analytical techniques for VLSI failure analysis , 1990, 28th Annual Proceedings on Reliability Physics Symposium.

[17]  Randall P. Sadowski,et al.  Introduction to Simulation Using Siman , 1990 .

[18]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[19]  Wojciech Maly,et al.  Yield estimation model for VLSI artwork evaluation , 1983 .

[20]  James A. Cunningham,et al.  Management: Using the learning curve as a management tool: The learning curve can help in preparing cost reduction programs, pricing forecasts, and product development goals , 1980, IEEE Spectrum.