Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature

This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behav- ior and with high Ion/Ioff ratio (∼ 10 5 ), as well as low Drain- Induced Barrier Lowering of ∼70 mV/V. Index Terms—CMOS technology, gate-all-around (GAA), sub- threshold swing (SS), top-down, tunneling field-effect transistor (TFET), vertical silicon nanowire (NW) (SiNW).

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