Restoring and non-restoring array divider designs in Quantum-dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is a very high speed, extra low power and extremely dense technology for implementing computing architectures which encodes binary logics through configuration of charges amongst quantum dots. Several studies of adders and multipliers in QCA have been proposed, whereas QCA divider design and implementation is a rather unexplored research area. In this paper the earliest designs for QCA dividers, which explore the restoring and non-restoring array dividers, considered as the best possible dividers, are introduced. These designs use well-organized arithmetic components as their basic construction parts and take some design rules into consideration which make them reliable and more robust against noise. These dividers with their design considerations and constraints are introduced step by step. Moreover, these designs are probed in terms of complexity, clocking and latency. QCADesigner, a simulation tool for QCA circuits, is used to check circuits' layout and functionality.

[1]  C. Lent,et al.  Clocked molecular quantum-dot cellular automata , 2003 .

[2]  G.A. Jullien,et al.  A method of majority logic reduction for quantum cellular automata , 2004, IEEE Transactions on Nanotechnology.

[3]  T. J. Fountain,et al.  A memory design in QCAs using the SQUARES formalism , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[4]  Keivan Navi,et al.  Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata , 2014, J. Low Power Electron..

[5]  Zhong Yi,et al.  On behavior of two-dimensional cellular automata with an exceptional rule , 2009, Inf. Sci..

[6]  W. Porod Quantum-Dot Devices and Quantum-Dot Cellular Automata , 1997 .

[7]  Brandon Dixon,et al.  A Characterization of Important algorithms for Quantum-Dot Cellular Automata , 1999, Inf. Sci..

[8]  John Lach,et al.  Modeling QCA for area minimization in logic synthesis , 2003, GLSVLSI '03.

[9]  Omid Kavehei,et al.  A novel low-power full-adder cell for low voltage , 2009, Integr..

[10]  Fabrizio Lombardi,et al.  HDLQ: A HDL environment for QCA design , 2006, JETC.

[11]  C. Lent,et al.  Demonstration of a six-dot quantum cellular automata system , 1998 .

[12]  K. Navi,et al.  Logic Optimization for Majority Gate-Based Nanoelectronic Circuits Based on Genetic Algorithm , 2007, 2007 International Conference on Electrical Engineering.

[13]  P. D. Tougaw,et al.  AN ALTERNATIVE GEOMETRY FOR QUANTUM-DOT CELLULAR AUTOMATA , 1999 .

[14]  E. Swartzlander,et al.  Adder Designs and Analyses for Quantum-Dot Cellular Automata , 2007, IEEE Transactions on Nanotechnology.

[15]  Michael A. Wilson,et al.  Nanotechnology: Basic Science and Emerging Technologies , 2002 .

[16]  Keivan Navi,et al.  Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata , 2015, Microelectron. J..

[17]  G. Tóth,et al.  QUASIADIABATIC SWITCHING FOR METAL-ISLAND QUANTUM-DOT CELLULAR AUTOMATA , 1999, cond-mat/0004457.

[18]  S. Srivastava,et al.  Are QCA cryptographic circuits resistant to power analysis attack? , 2012, IEEE Transactions on Nanotechnology.

[19]  P. D. Tougaw,et al.  Logical devices implemented using quantum cellular automata , 1994 .

[20]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[21]  Rui Zhang,et al.  Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[22]  Wei Wang,et al.  Quantum-dot cellular automata adders , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

[23]  Wolfgang Porod,et al.  Quantum-dot cellular automata : computing with coupled quantum dots , 1999 .

[24]  P. D. Tougaw,et al.  A device architecture for computing with quantum dots , 1997, Proc. IEEE.

[25]  Mostafa Rahimi Azghadi,et al.  A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter , 2009, Microelectron. J..

[26]  Mohsen Hayati,et al.  Design of novel efficient adder and subtractor for quantum-dot cellular automata , 2015, Int. J. Circuit Theory Appl..

[27]  T.J. Dysart,et al.  > Replace This Line with Your Paper Identification Number (double-click Here to Edit) < 1 , 2001 .

[28]  Ramesh Karri,et al.  Quantum-Dot Cellular Automata Design Guideline , 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[29]  Graham A. Jullien,et al.  Design Tools for an Emerging SoC Technology: Quantum-Dot Cellular Automata , 2006, Proceedings of the IEEE.

[30]  E.E. Swartzlander,et al.  Modular Design of Conditional Sum Adders Using Quantum-dot Cellular Automata , 2006, 2006 Sixth IEEE Conference on Nanotechnology.

[31]  T. Hiroshima Decoherence and entanglement in two-mode squeezed vacuum states. , 2000, quant-ph/0006100.

[32]  G Varga Investigation of possibility of high temperature quantum-dot cellular automata , 2007 .

[33]  Mostafa Rahimi Azghadi,et al.  Five-Input Majority Gate, a New Device for Quantum-Dot Cellular Automata , 2010 .

[34]  John C. Lusth,et al.  Eliminating non-logical states from linear quantum-dot-cellular automata , 2001 .

[35]  A. S. Molahosseini,et al.  Efficient reverse converter designs for the new 4-moduli sets {2n - 1, 2n, 2n + 1, 22n+1 - 1} and {2n - 1, 2n + 1, 22n, 22n + 1} based on new CRTs , 2010 .

[36]  Keivan Navi,et al.  Efficient QCA Exclusive-or and Multiplexer Circuits Based on a Nanoelectronic-Compatible Designing Approach , 2014, International scholarly research notices.

[37]  Zine-Eddine Abid,et al.  Low power multipliers based on new hybrid full adders , 2008, Microelectron. J..

[38]  N. Ranganathan,et al.  Design of Testable Reversible Sequential Circuits , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[39]  Qishan Zhang,et al.  Logic optimization for majority gate-based nanoelectronic circuits , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[40]  Eric Peskin,et al.  A QCA Implementation of a Configurable Logic Block for an FPGA , 2006, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006).

[41]  Vassil S. Dimitrov,et al.  Computer arithmetic structures for quantum cellular automata , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[42]  Wolfgang Porod,et al.  Quantum cellular automata , 1994 .

[43]  Keivan Navi,et al.  Arithmetic Circuits of Redundant SUT-RNS , 2009, IEEE Transactions on Instrumentation and Measurement.

[44]  Earl E. Swartzlander,et al.  Serial Parallel Multiplier Design in Quantum-dot Cellular Automata , 2007, 18th IEEE Symposium on Computer Arithmetic (ARITH '07).

[45]  G.A. Jullien,et al.  High Level Exploration of Quantum-Dot Cellular Automata (QCA) , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

[46]  Omid Kavehei,et al.  Efficient Reverse Converter Designs for the New 4-Moduli Sets $\{2^{n} -1, 2^{n}, 2^{n} +1, 2^{2n + 1}-1\}$ and $\{2^{n} -1, 2^{n} +1, 2^{2n}, 2^{2n} +1\}$ Based on New CRTs , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[47]  Gary H. Bernstein,et al.  Experimental demonstration of a leadless quantum-dot cellular automata cell , 2000 .

[48]  Vassil S. Dimitrov,et al.  RAM Design Using Quantum-Dot Cellular Automata , 2003 .

[49]  Mostafa Rahimi Azghadi,et al.  A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders , 2007, ArXiv.

[50]  C. Lent,et al.  Quantum‐Dot Cellular Automata at a Molecular Scale , 2002 .

[51]  G. Tóth,et al.  Quantum computing with quantum-dot cellular automata , 2001 .

[52]  Earl E. Swartzlander,et al.  Adder and Multiplier Design in Quantum-Dot Cellular Automata , 2009, IEEE Transactions on Computers.

[53]  Saket Srivastava,et al.  QCAPro - An error-power estimation tool for QCA circuit design , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[54]  Mi Lu Arithmetic and logic in computer systems , 2004 .

[55]  Xiaohui Zhao,et al.  A comparative analysis and design of quantum-dot cellular automata memory cell architecture , 2012, Int. J. Circuit Theory Appl..

[56]  Keivan Navi,et al.  Design of Efficient and Testable n-Input Logic Gates in Quantum-Dot Cellular Automata , 2013 .