Process variation immune dopingless dynamically reconfigurable FET
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[1] M. J. Kumar,et al. Doping-Less Tunnel Field Effect Transistor: Design and Investigation , 2013, IEEE Transactions on Electron Devices.
[2] Jawar Singh,et al. Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications , 2015, IEEE Transactions on Electron Devices.
[3] Qin Zhang,et al. Low-Voltage Tunnel Transistors for Beyond CMOS Logic , 2010, Proceedings of the IEEE.
[4] C. Salm,et al. The Charge Plasma P-N Diode , 2008, IEEE Electron Device Letters.
[5] G. De Micheli,et al. Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.
[6] Nisha Checka,et al. FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics , 2010, Proceedings of the IEEE.
[7] K. Nayak,et al. DC Compact Model for SOI Tunnel Field-Effect Transistors , 2012, IEEE Transactions on Electron Devices.
[8] H. Grubin. The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.
[9] Stefan Slesazeck,et al. Reconfigurable silicon nanowire transistors. , 2012, Nano letters.
[10] P. Dobson. Physics of Semiconductor Devices (2nd edn) , 1982 .
[11] Jawar Singh,et al. Charge-Plasma Based Process Variation Immune Junctionless Transistor , 2014, IEEE Electron Device Letters.
[12] A Dynamically Configurable Silicon Nanowire Field Effect Transistor based on Electrically Doped Source/Drain , 2014, 1412.4975.
[13] Adrian M. Ionescu,et al. Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.