VLSI design and verification of the Imagine processor

The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford University and Texas Instruments in a 1.5 V 0.15 /spl mu/m process with five layers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design a high-performance media processor in a modern ASIC flow.

[1]  David G. Chinnery,et al.  Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design , 2002 .

[2]  William J. Dally,et al.  Imagine: Media Processing with Streams , 2001, IEEE Micro.

[3]  I. Chen,et al.  A sub-0.1 /spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V) , 1996, International Electron Devices Meeting. Technical Digest.

[4]  Thomas Kutzschebauch,et al.  Regularity driven logic synthesis , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[5]  Rajesh K. Gupta,et al.  Extraction of functional regularity in datapath circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  William J. Dally,et al.  Digital systems engineering , 1998 .

[7]  C. A. J. van Eijk,et al.  Regular layout generation of logically optimized datapaths , 1997, ISPD '97.