Optimal design of clock trees for multigigahertz applications
暂无分享,去创建一个
[1] Yehea I. Ismail,et al. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[2] D. A. Dunnett. Classical Electrodynamics , 2020, Nature.
[3] K. Banerjee,et al. Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
[4] James D. Meindl,et al. A physical model for the transient response of capacitively loaded distributed rlc interconnects , 2002, DAC '02.
[5] Mattan Kamon,et al. FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.
[6] K.A. Jenkins,et al. A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).
[7] Takayasu Sakurai,et al. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .
[8] Rafael Escovar,et al. Transmission line design of clock trees , 2002, ICCAD 2002.
[9] T.H. Lee,et al. A 600 MHz superscalar RISC microprocessor with out-of-order execution , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[10] James D. Meindl,et al. Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks , 2000 .
[11] Robert W. Dutton,et al. A fast analytical technique for estimating the bounds of on-chip clock wire inductance , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).
[12] Gregory A. Northrop,et al. Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors , 1999, IBM Journal of Research and Development.
[13] Frederick Warren Grover,et al. Inductance Calculations: Working Formulas and Tables , 1981 .