Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

The conventional switched-capacitor amplifier faces design tradeoffs between settling accuracy and noise, in that high settling accuracy demands wide bandwidth but at the sacrifice of noise performance. In fact settling accuracy and noise exhibit different time dependence, which can be exploited to optimize the overall performance. Settling accuracy is determined by average bandwidth in the whole amplification phase, whereas the output noise of interest is determined by the bandwidth near the end of the phase. The proposed amplifier divides the amplification phase into two sub-phases. The first sub-phase starts with high bandwidth and high slew rate to approach the final value quickly. In the second sub-phase, the bandwidth can be significantly reduced, achieving the target settling accuracy but with much lower noise. This division allows the settling accuracy, noise, slew rate, and DC gain to be designed independently. A test chip is fabricated in a 65 nm CMOS process and operates at 90 MS/s. Measurements demonstrate that the proposed amplifier achieves 45% noise power reduction in the amplification phase along with improved linearity and lower power consumption, when compared with the conventional amplifier.

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