Challenges for low-k1 lithography in logic devices by source mask co-optimization

Through simulation and experiment, we evaluate the performance of process window improvement by source only optimization, mask only optimization or source mask co-optimization. From the results, we demonstrate that SMO is the most effective, and free-form source application is also effective. Additionally, it is found that SMO with calibrated resist model is very predictable. We then show that SMO application provides reasonable process window for 28-nm node and 22-nm node.