INPUT-FREE CASCODE Vthn AND Vthp EXTRACTOR CIRCUITS

Input-free NMOS and PMOS V th (threshold voltage) extractor circuits using cascode structure to eliminate the error caused by body effect are presented. The extracted Vth for NMOS and PMOS is referenced to ground and VDD respectively. Both NMOS and PMOS Vth extractor have high accuracy of almost 100% from the Hspice simulation. The NMOS and PMOS extractor circuits have been simulated in Hspice using TSMC 0.35µm CMOS technology at 2V and 2.9V power supply with low power consumption of 0.29mW and 0.44mW respectively.