Abstract The current saturation phenomena in the junction-gate field-effect transistor is analyzed using a two-section model for the conduction channel (a neutral and a depleted section) and the depletion model in the gate-junction transition region. The electric field along the channel, the electrostatic potential and the drain conductance are matched at the boundary of the two sections. Discontinuities of the drain current and conductance vs. the drain voltage characteristics near the drain current saturation points, which occurred in the simple matching procedure employed by Shockley, are removed. The computed drain resistance shows approximately a linear dependence on the drain voltage in the saturation region which is also demonstrated by the asymptotic solutions of large L/D (channel length/physical channel width), and it is proportional to L/D . Two impurity concentration profiles are studied which are the step-step (or abrupt) and the step-linear profiles for the double gate device structures. Experimental measurements of the saturation drain R-V characteristics for many silicon devices of both large (about 10) and small (about 1.5) L/D ratios are in good agreement with the theoretical analysis.
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