A low-power 0.13/spl mu/m CMOS OC-48 SONET and XAUI compliant SERDES

The design of a continuous rate octal 1.0 to 3.2 Gb/s serializer/deserializer circuit that meets SONET and XAUI requirements is presented. The performance of the SERDES surpasses stringent OC-48 jitter generation and tolerance specifications. This is achieved with the use of a master-slave PLL tuning scheme and meticulous attention to layout and isolation techniques. Implemented in a 0.13 /spl mu/m digital CMOS technology, the part exhibits less than 5 mUI r.m.s. jitter and the 1.2 mm/sup 2/ transceiver dissipates 160 mW.

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