A New Design and Implementation of the Butterfly Unit on FPGA

This paper presents a new method to implement the butterfly unit of FFT processor, based on the coordinate transformation and CORDIC algorithm. The butterfly unit uses less resource and reaches higher speed, also can be configured by parameter and satisfied by the real time operations. Finally, it can work on the frequency of 50 MHz after the design is downloaded to a chip EP2C20F484C7. Key Words-butterfly unit; CORDIC algorithm; pipeline; FPGA