Process variation aware DRAM (Dynamic Random Access Memory) design using block-based adaptive body biasing algorithm
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[1] Marios C. Papaefthymiou,et al. Block-based multi-period refresh for energy efficient dynamic memory , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
[2] Sani R. Nassif,et al. Modeling and analysis of manufacturing variations , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).
[3] B.C. Paul,et al. Process variation in embedded memories: failure analysis and variation aware architecture , 2005, IEEE Journal of Solid-State Circuits.
[4] Gu-Yeon Wei,et al. Process Variation Tolerant 3T1D-Based Cache Architectures , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[5] S.R. Nassif. Within-chip variability analysis , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[6] T. Ghani,et al. Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).
[7] Chung Lam. Cell Design Considerations for Phase Change Memory as a Universal Memory , 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
[8] Shyh-Chyi Wong,et al. Modeling of interconnect capacitance, delay, and crosstalk in VLSI , 2000 .
[9] Bruce Jacob,et al. Memory Systems: Cache, DRAM, Disk , 2007 .
[10] J. Torrellas,et al. VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects , 2008, IEEE Transactions on Semiconductor Manufacturing.
[11] T. Fujita,et al. A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[12] James D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.
[13] Kaushik Roy,et al. Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).
[14] Norbert Wehn,et al. Embedded DRAM Development: Technology, Physical Design, and Application Issues , 2001, IEEE Des. Test Comput..
[15] K. Roy,et al. Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[16] 杨银堂,et al. A statistical RCL interconnect delay model taking account of process variations , 2011 .
[17] R. Ng. Memory-fast computer memories , 1992, IEEE Spectrum.
[18] Young,et al. Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic Designs , 1997, 1997 Symposium on VLSI Technology.
[19] K. Roy,et al. Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS , 2007, IEEE Journal of Solid-State Circuits.
[20] Kaushik Roy,et al. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[21] Kaushik Roy,et al. Statistical design and optimization of SRAM cell for yield enhancement , 2004, ICCAD 2004.
[22] Tadahiro Kuroda,et al. Variable Threshold-Voltage (VT) Scheme , 1996 .
[23] David Blaauw,et al. Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[24] Azadeh Davoodi,et al. Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[25] Madhu Mutyam,et al. Working with process variation aware caches , 2007 .
[26] Kaushik Roy,et al. Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring , 2005, IEEE International Conference on Test, 2005..
[27] Jinjun Xiong,et al. Robust Extraction of Spatial Correlation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[28] Eric Rotenberg,et al. Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..
[29] Marios C. Papaefthymiou,et al. Block-based multiperiod dynamic memory design for low data-retention power , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[30] S. Narendra,et al. 1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[31] Kaushik Roy,et al. A process-tolerant cache architecture for improved yield in nanoscale technologies , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[32] M. Horiguchi,et al. Redundancy techniques for high-density DRAMs , 1997, 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon.
[33] S. E. Schuster. Multiple word/bit line redundancy for semiconductor memories , 1978 .
[34] Kaushik Roy,et al. Process variation in nano-scale memories: failure analysis and process tolerant architecture , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).
[35] Avesta Sasan,et al. Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[36] Victor Chin,et al. Cache on an Itanium Microprocessor , 2002 .
[37] Gaofeng Wang,et al. On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
[38] D. Sylvester,et al. A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[39] Sanghamitra Roy,et al. Process variation aware DRAM design using block based adaptive body biasing algorithm , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).
[40] David Blaauw,et al. Statistical Analysis and Optimization for VLSI: Timing and Power , 2005, Series on Integrated Circuits and Systems.
[41] Howard Leo Kalter,et al. A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC , 1990 .
[42] Onur Mutlu,et al. Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.
[43] Kazuaki Murakami,et al. Optimizing the DRAM refresh count for merged DRAM/logic LSIs , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).
[44] Jun Yang,et al. Variation-tolerant non-uniform 3D cache management in die stacked multicore processor , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[45] K. Sunouchi,et al. A sub-0.1 /spl mu/m circuit design with substrate-over-biasing [CMOS logic] , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[46] G. Ono,et al. A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[47] Costas J. Spanos,et al. Modeling within-die spatial correlation effects for process-design co-optimization , 2005, Sixth international symposium on quality electronic design (isqed'05).
[48] Vivek De,et al. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[49] Richard Veras,et al. RAIDR: Retention-aware intelligent DRAM refresh , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[50] Sherief Reda,et al. Within-die process variations: How accurately can they be statistically modeled? , 2008, 2008 Asia and South Pacific Design Automation Conference.