Impact of parasitic elements on the spurious triggering pulse in synchronous buck converter

Limiting the spurious triggering pulse in the gate-source voltage of the lower MOSFET during the turn-on transition of the upper MOSFET is mandatory to prevent substantial switching loss and even shoot-through in the synchronous buck converter. This paper conducts an exhaustive investigation into the impact of the inherent parasitic elements on the spurious triggering pulse to facilitate a reliability-oriented design. An analytical model that considers the parasitic capacitances and inductances, reverse recovery characteristics of the body diode and the interaction between the upper and the lower MOSFETs is established to quantify this pulse. The spurious triggering pulse is found to stem from the induced increase in the gate voltage and the induced decrease in the source voltage. Variation in the magnitude of the spurious triggering pulse in regard to each parasitic element is identified accordingly. Experimental results of a practical synchronous buck converter affirm the theoretical analysis.

[1]  Weimin Zhang,et al.  Analysis of the switching speed limitation of wide band-gap devices in a phase-leg configuration , 2012, 2012 IEEE Energy Conversion Congress and Exposition (ECCE).

[2]  Toni López,et al.  Power MOSFET Technology Roadmap Toward High Power Density Voltage Regulators for Next-Generation Computer Processors , 2012, IEEE Transactions on Power Electronics.

[3]  Weifeng Sun,et al.  Analysis and design optimization of brushless DC motor's driving circuit considering the Cdv/dt induced effect , 2010, 2010 IEEE Energy Conversion Congress and Exposition.

[4]  T. Lopez,et al.  Impact of gate voltage bias on reverse recovery losses of power MOSFETs , 2006, Twenty-First Annual IEEE Applied Power Electronics Conference and Exposition, 2006. APEC '06..

[5]  S. Mazumder,et al.  DV/DT related spurious gate turn-on of bidirectional switches in a high-frequency cycloconverter , 2005, IEEE Transactions on Power Electronics.

[6]  B. Yang,et al.  Effect and utilization of common source inductance in synchronous rectification , 2005, Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, 2005. APEC 2005..

[7]  G. Stojcic,et al.  Characterization of $Cdv/dt$ Induced Power Loss in Synchronous Buck DC–DC Converters , 2004, IEEE Transactions on Power Electronics.

[8]  M. Melito,et al.  Advanced characterization of low-voltage power MOSFETs in synchronous-rectifier buck-converter applications , 2003, 38th IAS Annual Meeting on Conference Record of the Industry Applications Conference, 2003..

[9]  Thomas Wu CDV/DT INDUCED TURN-ON IN SYNCHRONOUS BUCK REGULATORS , 2001 .

[10]  Peng Xu,et al.  Investigation of candidate VRM topologies for future microprocessors , 2000 .